The performance of a bus protocol directly impacts the overall performance of an integrated circuit and/or an integrated circuit system. Known bus protocols have a problem wherein an external bus arbiter is not always able to determine a point at which bus ownership may be transferred to another master when the current master is performing a series of back-to-back locked transfer sequences in a synchronous bus system. The occurrence of a locked transfer will typically be denoted in known systems with a LOCK signal which indicates that the current master intends the transfer or sequence of transfers to be atomic (i.e. not capable of being separated). However, if the master has several series of these atomic locked sequences back-to-back, and if an external arbiter could be aware of the abutments of these atomic sequences, it would be perfectly permissible for the external arbiter to take the bus ownership away from the master and give it to a more needy master at the interface between the sequences.
Known bus protocols could not prevent the starvation of the other bus masters during times when a bus master is performing a long series of back-to-back locked transfers. FIG. 4 shows the operation of the synchronous bus performing two consecutive locked sequences with no intervening bus clocks. From FIG. 4 it can be seen that an external arbiter cannot determine the difference between a single, many-transfer locked sequence and multiple sequences that have no intervening bus clocks. This is a problem when the arbiter needs to let another bus master have the bus, but needs to preserve the locked nature of the linked locked sequences without interruption. To guarantee no disruption of the locked sequences the arbiter is forced to wait for the negation of LOCK before negating BG (bus grant) to the master currently using the bus. Since LOCK is not negated between sequences, the current master can effectively monopolize the bus by running back-to-back locked sequences.
Note that known bus protocols require that LOCK be asserted through the termination of the last transfer in a locked sequence. LOCK must remain asserted for all transfers within a locked sequence since a slave may signal the need for a transfer retry on any transfer.
One known bus protocol tried to fix the above-described problem by the addition of one or two dead clocks between locked sequences. These dead clocks were found to either end up breaking a locked sequence or had the undesirable side-effect of lowering performance and increasing bus latency for other masters with urgent requests. To further solve the above-stated problem, bus protocols incorporated a last locked bus cycle status indicator (LOCKE) to allow the arbiter to negate BG to the master during the last transfer of a locked sequence and overlap arbitration with the transfer. However, there is a case during a bus cycle retry where the external bus arbiter must asynchronously reassert BG to preserve the locked integrity of the bus transactions. FIG. 5 shows this case. Note in FIG. 5 the bus arbiter negates BG in bus cycle 2 (BC2) when it sees LOCKE asserted and BR (bus request) negated. However, a transfer retry is signaled (TRA asserted) and to prevent the breaking of a locked sequence the external bus arbiter must asynchronously reasserted BG. This makes the design of an external bus arbiter which solves the above-stated problem very difficult since the retry signal (TRA) must also now be sampled at a very fast rate. This is most likely impossible at very high processor clock frequencies and impossible for totally synchronous designs.
Known overlapped bus arbitration protocols also have a problem of denoting the end of bus tenure by a current bus master while a second master is starting to use the bus without resorting to asynchronous, self-timed, or tick based logic internal to a bus master. A known protocol for handling this problem is the Bus Busy protocol. Problems occur at very high bus frequencies using the Bus Busy (BB) protocol. FIG. 1 shows the operation of the Bus Busy protocol in a known system. Normally in a system, the primary master Bus Busy (PM.sub.13 BB*) and alternate bus master Bus Busy (AM.sub.13 BB*) signals will be tied together and pulled-up with a resistor to Vdd, but these signals have been broken out here to show the potential for Bus Busy signal contention at bus mastership transfer times. The system of FIG. 1 uses a tick based internal clock and attempts to solve the above-stated problem by separating the turn-on and turn-off times by a dead tick. A tick is a fraction of a full clock period. The dead tick method may work at slow bus frequencies but will not work at high bus frequencies because of the narrower tick times and RC constant of the bused Bus Busy signal.